About the Course:

This Session is mainly designed for beginners / Layout Designers & Circuit Designers (Undergrad Students, Masters Students, PHD, Layout newbies 0-6 yrs. exp). It is very important to understand ,read and be able to write a netlist.  For circuit designers it helps in debugging simulation runs / for Layout Engineers it helps in debugging and fixing LVS and for the Beginners it helps in understanding the design and Layout concepts . We have seen many scenarios in our experience in which a Layout / Circuit guy is  expected to decode and understand a netlist . To upskill them in debugging we created this session which will teach them , How to write a Spice netlist ? , taking 2 test cases , 1 Digital and 1 Analog , describing the Flat netlist and Hierarchical as well .This session will certainly help you UNDERSTAND and do your job better . 

 

Who can Benefit from this course?

- Undergrad students, Master's Students, PHD candidates, Faculties, technology enthusiasts, Job seekers, it would help in interview preparation

- Working Professionals who would want to enhance their skill in profiles like (ASIC design, Analog Circuit Design, Analog IC layout Design, Physical Design, Physical Verification, Standard cell Layout Design, Analog Layout Design, Memory Layout Design & IO Layout Design).

- Things what you learn in this session, would help you improve the quality of work what you deliver. 

- Candidates who are hungry for Knowledge and would want to know the Whole ASIC implementation. 

 

Topics Covered in this Session:

- What is a Schematic/ symbol/ Netlist/ Model file?

- Device representations and parameters

- Writing a Netlist /. Subckt creation?

     oTest Case 1: Digital Module

       Transistor level implementation of Gates

       Hierarchical Implementation of Half Adder

     oTest Case 2: Analog Module

       Transistor level implementation of OPAMP

       Hierarchical implementation of LDO

- Circuit file for simulation / Testbench

- Types of Netlists