About the Course:

This Course is designed for All the VLSI engineers who are into Analog Layout Design / Physical Design / Physical Verification/ Junior or Fresh Graduates. what happens after a Layout engineer makes a design LVS / DRC clean .Even after design specks are met, before the layouts are handed over to the PD team. OR before being releasing the design to the customer. There is a list sanity and Quality checks which need to be verified .To have a complete end to end understanding of physical verification, this course gives you the finishing touch.

 

Who can Benefit from this course?

- Working Professionals who would want to enhance their skill in profiles like (ASIC design, Analog Circuit Design, Analog IC layout Design, Physical Design, Physical Verification, Standard cell Layout     Design, Analog Layout Design, Memory Layout Design & IO Layout Design).

- Undergrad students, Master's Tech Students, PHD candidates, Faculties, technology enthusiasts, Job seekers, it would help in interview preparation

- Things what you learn in this session, would help you improve the quality of work what you deliver. 

- Candidates who are hungry for Knowledge and would want to know the Whole ASIC implementation. 

 

The topics covered are as below : 

- What are sanity checks ?  

- Why are sanity checks needed?

- Sanity checks in detail 

- What are QA checks ?

- Why are QA checks needed? 

-  QA checks in detail

- Waivers for checks

- Design hand-off

- IP release