About the Course :

In these self-paced sessions, you would be learning the concepts of ASIC Physical Verification in detail. Its significance and the Flows. This course would help you to understand Physical Verification in depth and not just fix DRCs and LVS issues. There is a lot more to Physical Verification, which goes in the background. Every setting done by the CAD / Enablement team impacts the way the execution of the rule from the foundry.  Making you understand the concepts and giving you the tips and tricks based on our experience to help you do your Job better.

Who can Benefit from this course ? :

- Undergraduate students, Master's Students , PHD candidates, Faculties, technology enthusiasts ,Job seekers , it would help in interview preparation

- Working Professionals who would want to enhance their skill in profiles like (ASIC design , Analog Circuit Design, Analog IC layout Design, Physical Design, Physical Verification, Standard cell Layout     Design, Analog Layout Design, Memory Layout Design & IO Layout Design).

- Things what you learn in this session, would help you improve the quality of work what you deliver . 

- Candidates who are hungry for Knowledge and would want to know the Whole ASIC implementation .

The topics covered are as below :

- What is Physical Verification? Its Significance ?

- Tools used and Glossary

- DRC Flow

- Significance of DRC Rule checks 

- Examples of DRCs and inputs to fix them

- What is LVS Flow ?

- Significance of LVS 

- What happens in the background when you run LVS ?

- ERC  Errors , significance of Power connections , Extraction Errors

- Types of LVS Errors and How to Debug them?

- IP Closure Guidelines