About the Course:

This session is specifically designed for working professionals new to FinFETs and layout engineers looking to strengthen their understanding of FinFET layouts. Drawing from our extensive experience with FinFETs, we address a variety of challenges you may encounter during layout design. The course discusses precautionary measures to help your complete layouts efficiently and minimize rework. By adopting a systematic approach, FinFET layouts can be completed more quickly, avoiding the common DRC issues that can frustrate layout engineers. This session provides comprehensive guidance on FinFET layout methodologies, covering key DRC rules that often create bottlenecks during tape-outs. Additionally, we explore advanced concepts such as double patterning, matching, LUP, EM/IR, Self heating and more.

Some tips and tricks which would help the aspiring Engineers to improve their layout skills. and do their job in an organized way to become an Efficient layout engineer. 

Who can Benefit from this course?

- Undergrad students, Master's Students, PHD candidates, Faculties, technology enthusiasts, Job seekers, it would help in interview preparation

- Working Professionals who would want to enhance their skill in profiles like (ASIC design, Analog Circuit Design, Analog IC layout Design, Physical Design, Physical Verification, Standard cell Layout Design, Analog Layout Design, Memory Layout Design & IO Layout Design).

- Things what you learn in this session, would help you improve the quality of work what you deliver. 

- Candidates who are hungry for Knowledge and would want to know the Whole ASIC implementation. 

are hungry for Knowledge and would want to know the Whole ASIC implementation. 

 The topics covered are as below: 

- Introduction to Finfets

- Layout Effort: Legacy node comparison

- Layout perspective

• Finfet Layout Cross section / 3D View
• Grids (Fin/ Poly)
• Finfet Layout Top View

- Finfet Layout Guidelines

• Addressing Fin/ OD issues
• Addressing POLY issues
• Addressing LUP issues
• Usage of metals
• Using Device Pcell options
• EM / IR precautions

- Double Patterning challenges

• What is Double Patterning?
• Why do we go for Double Patterning?
• Types of patterning trends
• Double Patterning in metals & Vias
• DRC errors
• G0 errors 
• Voltage marker errors
• LVS errors

-  Usage of CUT layers

- Matching considerations and Dummies

- Usage of Vias

- EM/ IR precautions

- Dealing with Density challenges

• Balancing the colours
• Addressing Line Edge density issues 

- Follow a methodical approach - extended