About the Course:

This Session is mainly designed for working professionals who want to explore about Finfet Layouts. Even the beginners can get the feel and understanding of How different is Finfet from Planar CMOS? Since we have extensive expertise of working on finfets . we tend to share the knowledge of Do’s and Don’ts when you are working with finfet Layouts. Finfet Layouts when done in a methodical way can be done quicker avoiding the nightmare a layout engineer would face with DRCs.

A proper approach on finfet layout guidelines is covered in this session trying  to cover almost all the important DRCs which could form a bottleneck during your Tape-outs. We have also covered about Double patterning concepts. the precautions one needs to take to avoid getting into Max POLY density issue. Taking care of these things will certainly help you meet your deadlines  

There are certain rules and guidelines to be followed before you do the finfet layouts. Certain pre-requisites you need to follow, which would help you do the layouts better and some precautions one needs to take to avoid the re-work. Some tips and tricks which would help the aspiring Engineers to improve their layout skills. and do their job in an organized way to become an Efficient layout engineer. 

Who can Benefit from this course?

- Undergrad students, Master's Students, PHD candidates, Faculties, technology enthusiasts, Job seekers, it would help in interview preparation

- Working Professionals who would want to enhance their skill in profiles like (ASIC design, Analog Circuit Design, Analog IC layout Design, Physical Design, Physical Verification, Standard cell Layout Design, Analog Layout Design, Memory Layout Design & IO Layout Design).

- Things what you learn in this session, would help you improve the quality of work what you deliver. 

- Candidates who are hungry for Knowledge and would want to know the Whole ASIC implementation. 

are hungry for Knowledge and would want to know the Whole ASIC implementation. 

 

The topics covered are as below: 

- Introduction to Finfets

- Layout perspective highlighting the differences

• Grids
• Layout View

- Common layout Guidelines for Planar and Finfet technologies

- Finfet Layout Guidelines

• Addressing OD and POLY issues
• Addressing LUP issues
• Usage of metals
• Using Device Pcell options
• EM / IR precautions

- Double Patterning challenges

• Double Patterning metals  & Vias
• Double patterning DRC issues
• Addressing G0 errors 
• Double patterning Density issues
• Balancing the colours
• Addressing Line Edge density issues 

- Follow a methodical approach