About the Course:

This Session is mainly designed for beginners and experienced professionals who are interested in Analog layouts (Undergrad Students, Masters Students, PHD students, Layout professionals).  In CMOS, PMOS and NMOS are on the same substrate, isolating them becomes important to avoid latchup issues. physically and electrically. In designs where substrate noise is a concern, multiple voltage designs are used along with floating wells. It becomes important to have clarity of these concepts. The significance of guard rings, its limitations and How Deep-nwell comes to the rescue when dealing with Analog and Digital domains on the same substrate. We have tried to explain certain scenarios with some real time examples to give a better understanding. What techniques the Layout engineer needs to follow while dealing with all kinds of devices. Some precautions one needs to take to avoid the re-work. Lots of Deep sub-micron effects and its mitigation methods are discussed in this session. Some tips and tricks which would help the aspiring Engineers to improve their layout skills. and do their job in an organized way to become an Efficient layout engineer. 

Who can Benefit from this course?

- Undergrad students, Master's Students, PHD candidates, Faculties, technology enthusiasts, Job seekers, it would help in interview preparation

- Working Professionals who would want to enhance their skill in profiles like (ASIC design, Analog Circuit Design, Analog IC layout Design, Physical Design, Physical Verification, Standard cell Layout Design, Analog Layout Design, Memory Layout Design & IO Layout Design).

- Things what you learn in this session, would help you improve the quality of work what you deliver. 

- Candidates who are hungry for Knowledge and would want to know the Whole ASIC implementation. 

The topics covered are as below: 

-Device Isolation 

o Physical isolation

o Electrical isolation

-Types of Wells 

-Latchup / SCR circuit

-Substrate Noise 

-Guard Rings 

-Floating Well Connection

-Deep N-Well

-Isolation layers